/*
 * @Description  : the final mux for the alu,dataMem to the regfile 
 * @authorName   : GuoJi
 * @github       : https://github.com/guoji-kk
 * @gitee        : https://gitee.com/guoji13663585559
 * @email        : 13663585559@163.com
 * @version      : 1.0
 * @Date         : 2023-05-14 23:34:46
 * @LastEditTime : 2023-05-16 20:42:51
 */

module mux(a0,a1,op,out);
  	input op;
  	input [31:0]a0,a1;
  	output reg[31:0]out;
  
  	always@(*)begin
    		if(op) 
			out=a1;
    		else 
			out=a0;
    	end

  endmodule

